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up-down-counter
- up down counter by verilog
counter
- 本文介绍了基于FPGA的数字频率计的设计方法，设计采用硬件描述语言Verilog ，在软件开发平台ISE上完成，可以在较高速时钟频率（48MHz）下正常工作。该数字频率计采用测频的方法，能准确的测量频率在10Hz到100MHz之间的信号。-This article describes the FPGA-based digital frequency meter design method using hardware descr iption language Verilog, ISE on t
verilogClassicSamples
- verilog常用程序及其仿真结果整理，包括LCD，LED，AD采集，URAT，电子琴，电梯控制，自动售货机控制，出租车计价器，电子时钟，频率计，MPSK调制与解调-verilog common finishing process and its simulation results, including LCD, LED, AD collection, URAT, keyboard, elevator control, vending machine control, taxi meter,
report-of-digital-pluse-counter
- 某一大学里关于数字频率计的电子实验报告,内容详尽,含verilog源码-A university on the electronic digital frequency meter test reports, and detailed, with verilog source
counter
- 基于XILINX XC3S300的计数器程序，编程语言VERILOG-XILINX XC3S300 based counter program, programming language VERILOG
Verilog
- 基于verilog HDL编写的各种实例。。里面记载了计数器，全加器，等等的代码。-Based on various examples written in verilog HDL. . Recording the counter, full adder, and so the code.
counter
- 使用verilog实现低位的十进制计数，高位的十六进制计数，带有Modelsim仿真测试文件-verilog Modelsim
verilog.tar
- counter.v...its verilog code for counter
Counter
- 用VERILOG语言实现的74*163 计数器，代码十分简单易懂，适合数字逻辑电路实验的初学者-With the VERILOG language implementation of the 74* 163 counter, the code is very simple and easy to understand, suitable for digital logic circuit experiment for beginners
m60BCD
- 异步清零多位计数器，应用verilog编程v-counter verilog configuration
counter
- 在Quartus环境下verilog语言编写的一个4位加数器，选择的是一位位进位，是学习时序的好例子-Quartus environment verilog language of a four addend, the choice is a binary, is a good example to learn the timing
counter
- 计算数程序 verilog xilinx-Calculate the number of procedures Verilog xilinx
counter
- 利用verilog开发的计数器程序，比较基本，包含完整的工程-Use of the the verilog development of counter program, more basic, including complete engineering
counter
- there is a text file of code for 8 bit up counter in verilog.
LL
- verilog语言的计数器设计程序代码。-counter verilog language design code.
d10-counter
- 十位加法器，用verilog语言编写，适用于verilog学习。-10-bit adder, using Verilog language, applicable in verilog learning.
ex1
- johnson 计数器 verilog源代码-johnson counter verilog
frequency-counter
- 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompressi
Verilog_0-9999_counter
- 用Verilog语言实现的0-9999计数器-0-9999 counter Verilog language
digital-frequency-counter
- 基于FPGA的数字频率计，verilog hdl编写-digital frequency counter ，using verilog hdl